![]() ![]() ![]() red in 10s then turn to yello -> green again for high way else next_state = HRED_FGRE Įnd HRED_FYEL: begin // red on highway and yellow on farm way yellow for 3s, then red else next_state = HYEL_FRED Įnd HRED_FGRE: begin // red on highway and green on farm way State green else next_state = HGRE_FRED Įnd HYEL_FRED: begin // yellow on highway and red on farm way next state always posedge clk or negedge rst_n) Wire clk_enable // clock enable signal for 1s reg state, next_state Reg delay10s = 0, dela圓s1 = 0,dela圓s2 = 0,RED_count_en = 0,YELLOW_count_en1 = 0,YELLOW_count_en2 = 0 Rst_n // reset active low output reg light_highway, light_farm // output of lights // FPGA projects, VHDL projects, Verilog projects reg count = 0,count_delay = 0 Parameter HGRE_FRED = 2'b00, // Highway green and farm red HYEL_FRED = 2'b01, // Highway yellow and farm red HRED_FGRE = 2'b10, // Highway red and farm green HRED_FYEL = 2'b11 // Highway red and farm yellow input C, // sensor FPGA projects, VHDL projects, Verilog projects // Verilog project: Verilog code for traffic light controller module traffic_light(light_highway, light_farm, C, clk, rst_n) ![]()
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